1. Field of the Invention
The present invention relates to a pattern forming method and a semiconductor device manufactured by using the pattern forming method.
2. Description of the Related Art
In recent years, the technology of manufacturing a semiconductor device has progressed to arrive at the stage that a semiconductor device having a minimum processing size of 0.18 μm can be manufactured nowadays on a mass production basis. This prominent miniaturization has been achieved by drastic progress in fine pattern forming technologies such as mask processing technology, photolithography technology and etching technology.
In the era when the pattern size was sufficiently large, a planar shape of a desired LSI pattern was depicted as it was on a wafer as a design pattern so as to form a mask pattern having a high fidelity to the design pattern, and the mask pattern was transferred onto the wafer by a projecting optical system, followed by etching the underlying layer, thereby forming a desired LSI pattern substantially equal to the design pattern on the wafer.
However, with progress in the miniaturization of the pattern, it has been rendered difficult to form a pattern with high fidelity in each process, giving rise to the problem that the final finish pattern fails to conform with the design pattern. Particularly, in the lithography and etching processes, which are most important for achieving fine processing, a pattern layout arranged in the periphery of a desired pattern, i.e., the peripheral pattern environment, greatly affects the dimensional accuracy of the desired pattern.
Under the circumstances, proposed in, for example, Jpn. Pat. KOKAI Publication No. 9-319067 are an OPC (Optical Proximity Correction) technology, a PPC (Process Proximity Correction) technology, etc., in which a dummy pattern is imparted in advance to a design pattern for forming the size after the processing in a desired pattern so as to suppress the influence described above. The OPC technology noted above denotes the technology for correcting the change in size generated in the lithography process by a pattern. On the other hand, the PPC technology noted above denotes the technology for correcting not only the change in size generated in the lithography process but also the change in size generated by the mask and the etching process by a pattern.
In the case of employing OPC technology, it is certainly possible to suppress the process conversion difference, i.e., the difference between the resist size and the design size, derived from the pattern environment in the lithography process to a low level. However, even in the case of employing PPC technology, it was impossible in some cases to suppress completely the process conversion difference, i.e., the difference between the size after the etching and the resist size, derived from the pattern environment in the etching process. The process conversion difference in the etching process was generated mainly by two factors.
First of all, the process conversion difference was generated by the etched area in a large region hundreds of times as large as the region of the entire chip or the minimum pattern size that was to be processed. The technology of arranging a dummy pattern differing from a main pattern for controlling the area to be etched is disclosed in, for example, Japanese Patent Disclosure No. 2-236549, Japanese Patent Disclosure No. 3-180041, and Japanese Patent Disclosure No. 4-130709. In each of these prior arts, a dummy pattern is formed around a pattern that is to be processed in order to make the area to be etched within the chip as uniform as possible. In Japanese Patent Disclosure No. 3-180041 referred to above, a dummy pattern is arranged on an element separation region alone. On the other hand, in Japanese Patent Disclosure No. 4-130709 referred to above, a dummy pattern is arranged around an isolated pattern.
The second factor is the etching process conversion difference generated by only the distance between the pattern to be processed and the adjacent pattern. To be more specific, when a pattern is arranged in an isolated manner, the process size of the pattern after etching is rendered larger than the resist size after the lithography process. In order to suppress the conversion difference, it is necessary to make the size of the resist formed by the lithography process smaller than the desired size in view of the conversion difference generated in the etching process. However, the process margin that can be ensured by the lithography process is very small, with the result that it is very difficult to form a resist pattern smaller than the desired size and to ensure a required process margin. In other words, even in the case of employing PPC technology, it is very difficult to correct the increase in size in the isolated pattern derived from the etching process.